Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design

Journal of Low Power Electronics and Applications. 2011;1(2):277-302 DOI 10.3390/jlpea1020277

 

Journal Homepage

Journal Title: Journal of Low Power Electronics and Applications

ISSN: 2079-9268 (Print)

Publisher: MDPI AG

LCC Subject Category: Technology: Electrical engineering. Electronics. Nuclear engineering: Applications of electric power

Country of publisher: Switzerland

Language of fulltext: English

Full-text formats available: PDF, HTML

 

AUTHORS

Tony T. Kim
Rajendra P. Agarwal
Sudeb Dasgupta
Ramesh Vaddi

EDITORIAL INFORMATION

Blind peer review

Editorial Board

Instructions for authors

Time From Submission to Publication: 11 weeks

 

Abstract | Full Text

Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID) design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.