Partial Reset: An Alternative DFT Approach

VLSI Design. 1994;1(4):299-311 DOI 10.1155/1994/31646

 

Journal Homepage

Journal Title: VLSI Design

ISSN: 1065-514X (Print); 1563-5171 (Online)

Publisher: Hindawi Publishing Corporation

LCC Subject Category: Science: Mathematics: Instruments and machines: Electronic computers. Computer science

Country of publisher: Egypt

Language of fulltext: English

Full-text formats available: PDF, HTML, ePUB

 

AUTHORS

Ben Mathew (Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, USA)
Daniel G. Saab (Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, USA)

EDITORIAL INFORMATION

Blind peer review

Editorial Board

Instructions for authors

Time From Submission to Publication: 19 weeks

 

Abstract | Full Text

Design for testability (DFT) techniques reduce testing costs at the price of extra hardware. Among the many DFT techniques that have been proposed for this task are full scan, partial scan and hardware reset. In this paper we explore a relatively new DFT method, called partial reset. Reset lines are added to only a subset of the flip-flops and obtain reasonably high coverage. This approach has lower overhead in terms of test application time and hardware area when compared to previous ones. Further enhancement of the controllability is obtained by using multiple reset lines. The configuration of these multiple reset lines is described. This technique has been evaluated on the 1989 ISCAS sequential benchmark circuits and obtained favorable results.