An ARM-FPGA Hybrid Acceleration and Fault Tolerant Technique for Phase Factor Calculation in Spaceborne Synthetic Aperture Radar Imaging

Abstract

In the realm of real-time spaceborne synthetic aperture radar (SAR) imaging, the accurate and swift phase factors calculation (PFC) holds significant importance. This article introduces an innovative advanced RISC machines (ARM) field-programmable gate array (FPGA) hybrid acceleration technique designed to expedite the phase factor computation process of SAR imaging. By combing the strengths of ARM and FPGA, our approach achieves optimal performance. The proposed methodology strategically allocates the initial and intermediate calculations to ARM, while delegating the intricate exponential functions to FPGA. By incorporating a parallel four-channel coordinated rotation digital computer (CORDIC) structure and redundancy-based fault tolerant modules with error correction codes, the protection of soft errors is realized and the reliability is improved. By utilizing a modified three-tiered reconfigurable processing elements exchange network for fault tolerant CORDIC processors, the acceleration of computing time is realized and hardware overhead is reduced. A comprehensive prototype verification illustrates the method's efficacy for PFC in spaceborne SAR imaging. The evaluation of computational time and resource utilization unveils ARM's suitability for the initial two levels, while the complexities and precision of the third level warrant FPGA computing acceleration. Overall, this research advances a novel ARM-FPGA hybrid strategy that elevates phase factor computation in spaceborne SAR imaging, opening up avenues for efficient and dependable radar imaging applications.

Keywords

• Fault tolerance (FT)
• field programmable gate arrays (FPGA)
• hybrid integrated circuits (HICS)
• phase factor calculation (PFC)
• synthetic aperture radar (SAR)