IEEE Access (Jan 2025)
A Review on Frequency Compensation and Transient Enhancement Schemes of Flipped Voltage Follower LDO Regulators for SoC Applications
Abstract
The low dropout (LDO) regulator is an essential circuit in the wireless power module of any portable device. The power management integrated circuits demand low power, high performance LDO regulator. Designing the LDO regulators for the desired performance parameters is challenging since it has design trade-offs. The power reduction is one main design challenge in the LDO to make it suitable for low-power, high-performance applications. The output capacitor-less LDOs are attractive for system-on-chip (SoC) applications, however the removal of the external capacitor degrades its stability and transient responses. The flipped voltage follower (FVF) output capacitor-less LDO regulators gained attention due to its superior transient performance with less power, as this structure demands lesser quiescent current to achieve the same transient response compared to the conventional LDOs. To our knowledge, the FVF LDOs in terms of transient enhancement schemes and stability techniques are not yet reviewed to understand the challenges in these LDO designs to suit for SoC applications. This paper provides a comprehensive study of different types of FVF low dropout regulators, the compensation circuits used in these LDOs for the stability of feedback loop and different transient enhancement schemes to improve the settling time and to reduce the output voltage spikes. A capacitor-less FVF LDO regulator with improved settling time and PSR is proposed in this paper. The transient performance of the FVF LDOs are measured based on the figure of merits and stability in terms of the phase margin. The proposed FVF LDO achieves a settling time of $100 \ ns$ and PSR of $-31\ dB\text{@}1\ MHz$ . The design challenges of FVF LDOs to achieve the required specifications to use for wireless power module of battery-operated devices are also discussed.
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