Automated RTL Generator for Optimized Flop Repeater Network

Abstract

In all Hard IP (HIP) designs, there is a need for signals to travel from its source to destination module. To meet timing, they are flop repeated based on the floorplan of the design. Different signals have unique repetition requirements based on their functionality/timing criticality. Also signals may have single destination or multiple destinations. The flop repeater structure for each signal should be optimized so that it has minimum number of flops and timing is also met, to achieve desired targets for timing, area and power. This paper will show how we are creating optimized treestructure based on mathematical techniques and generating automated RTL for such repeater flop module. This submission presents a new tool ART (Auto Repeater Tool) that completely eliminates the manual effort/time required to generate functional, ready to plug-in RTL.

Keywords

• optimized repeater flop structure
• repeater
• flop
• automated rtl
• srep/tree
• logic design