Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

Ruibo Chen; Hongxia Liu; Wenqiang Song; Feibo Du; Hao Zhang; Jikai Zhang; Zhiwei Liu

doi:10.1186/s11671-020-03437-3

Nanoscale Research Letters (Nov 2020)

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

Ruibo Chen,
Hongxia Liu,
Wenqiang Song,
Feibo Du,
Hao Zhang,
Jikai Zhang,
Zhiwei Liu

Affiliations

Ruibo Chen: Key Laboratory for Wide-Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University
Hongxia Liu: Key Laboratory for Wide-Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University
Wenqiang Song: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China
Feibo Du: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China
Hao Zhang: Key Laboratory for Wide-Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University
Jikai Zhang: Key Laboratory for Wide-Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University
Zhiwei Liu: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China

DOI: https://doi.org/10.1186/s11671-020-03437-3
Journal volume & issue: Vol. 15, no. 1
pp. 1 – 6

Abstract

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Abstract Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

Published in Nanoscale Research Letters

ISSN: 1931-7573 (Print); 1556-276X (Online)
Publisher: SpringerOpen
Country of publisher: United Kingdom
LCC subjects: Technology: Electrical engineering. Electronics. Nuclear engineering: Materials of engineering and construction. Mechanics of materials
Website: https://www.springer.com/journal/11671

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