High‐speed serializer timing‐error detection circuit with enhanced verification reliability through floating state prevention

Abstract

Abstract This article presents a serializer (SER) timing‐error detection circuit that enhances the verification reliability of high‐speed wireline interfaces. A timing mismatch in the SER leads to bit errors during data transmission. To detect the timing error, the proposed design employs a set‐reset latch to self‐latch the detection result, improving the error detection accuracy, unlike the previously reported timing‐error detection design using a D flip‐flop. The prototype transmitter chip, fabricated using a 28‐nm CMOS process, was validated for accurate error detection across wide data rates ranging from 1.25 to 13 Gb/s, ensuring reliable high‐speed operation while efficiently handling timing mismatches across multiple SER stages.

Keywords

• error detection
• high‐speed integrated circuits
• transmitters