A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse

Abstract

This article presents a fully integrated bidirectional class-G digital Doherty switched capacitor transmitter (TX) and N-path Quadrature receiver (RX) in CMOS. Through sharing on-chip capacitor banks, typically occupying a major portion of the digital TX or RX chip area, as well as the RF passive matching networks, the overall size can be radically reduced. Moreover, the overall performance could be further improved by eliminating the need for an integrated T/RX switch and its corresponding loss and area overhead. The class-G operation is used within the Doherty TX to increase the output power and backoff efficiency, while the capacitive stacking technique is used in the RX to increase the voltage gain. A transformer network is used to present the optimum impedance for both the parallel Doherty TX and RX mode of operation, as well as the class-G Doherty active load modulation. As a proof-of-concept, the joint bidirectional class-G digital Doherty switched-capacitor TX and N-path Quadrature RX through capacitor bank sharing is implemented in a 45-nm CMOS SOI process. The TX demonstrates a $\text{P}_{\mathrm {out}}~1$ dB bandwidth (BW) of 1.6-3.1 GHz, a fractional BW >63%, and peak output power ( $\text{P}_{\mathrm {out}}$ ) of 22.5dBm at 2.4GHz. The peak drain efficiency (DE) of the TX is 49.5% at 1.8GHz and 41.5%/38.7%/31.6%/18.1% for the peak/2.5/6/12dB power back off (PBO) at 2.4GHz. The DE improvement compared to class-B PA is $1.24\times /1.51\times /1.72\times $ at 2.5/6/12dB PBO. The TX is measured using 64-QAM/20MHz modulation without the use of AM-PM pre-distortion or pattern based DPD. It achieves an excellent −27.1dB EVM, −31.31dBc ACLR, 14.6dBm average $\text{P}_{\mathrm {out}}$ and 25.8% average DE at 1.6GHz. The RX achieves a noise figure (NF) of 7.6dB at 2.2GHz and a conversion gain of 17dB with a 12 MHz bandwidth. In addition, the proposed RX front-end achieves $ < -60$ dBm LO leakage over the operating frequency range

Keywords

• Capacitor stacking
• class-G DPA
• CMOS
• digital front-end
• doherty
• linearity