Support Vector Machine reconfigurable hardware implementation on FPGA

Abstract

Support Vector Machine (SVM) is a robust Machine Learning (ML) algorithm used extensively in classification tasks. This work proposes a reconfigurable hardware implementation of the SVM classification algorithm for the linear and three kernel cases on FPGA. Efficient implementations of two generalization techniques, One-versus-All (OvA) and One-versus-One (OvO), to deal with multi-class problems are also realized on FPGA to overcome the binary nature of the SVM algorithm. The presented model is fully reconfigurable and can easily be adapted to any dataset with any number of classes or features. The results show that the proposed model excels in power efficiency, requires low area utilization, and reaches high performance up to 250.7 MHz. The two realized generalization methods, OvO and OvA, offer a trade-off between accuracy and hardware cost. OvA provides lower accuracy than OvO and is more affected by the data imbalance problem, which becomes more dominant as the number of classes increases; however, it is more resource-efficient than OvO. The proposed hardware design is realized and experimentally tested on FPGA for three different datasets, employing different linear and kernel SVM cases. The classification accuracy achieved by the reconfigurable hardware design matches the software simulation results.

Keywords

• Artificial intelligence
• Support Vector Machine
• Classification
• Floating point
• FPGA