Optimization and Design Considerations of GaN-Based Multi-Level TP PFC Converters

Abstract

Latest developments in low voltage wide-bandgap semiconductor technology have increased the popularity of single-phase multi-level (ML) totem pole (TP) power-factor correction (PFC) converters. Phase shifted flying capacitor based power stages offer several advantages, such as higher input current ripple frequency, smaller size inductor and differential mode (DM) filter, and usage of low voltage Gallium Nitride (GaN) devices with better figure-of-merit. Even though it has been proven that ML TP PFC converters have good power density and efficiency, the determination of optimal voltage levels and switching frequency requires a system-level optimization. This paper proposes an optimization framework for ML TP PFC converters, taking the power stage, thermal, DM filter, and magnetic designs, as well as practical design considerations, into account to determine the voltage-levels and switching frequency that minimize the power losses, cost and volume of the total system. To process output power of 3700W, the optimization tool suggests using a 4-Level GaN TP PFC topology switched at 45 kHz. The outcome of the tool has been compared with other fixed inductor current ripple designs, as well as optimized designs for 3-Level and 5-Level TP PFC converters in terms of cost, volume, and power losses. In accordance with the optimization results, a prototype of a 4L TP PFC rated at 3700 W is designed, which achieves a peak efficiency of 99.6% at 1 kW and> 99.1% efficiency under the full power range.

Keywords

• Ac/dc conversion
• multi-level
• optimization
• power factor correction
• totem-pole