Pipelined PAM-4 Direct Decision-Feedback Equalizer for Short-Reach Applications

Abstract

This paper presents a new quarter-rate 4-level pulse amplitude modulation (PAM-4) decision-feedback equalizer (DFE) architecture targeting short-reach and the onset of medium-reach applications. The proposed architecture utilizes the pipeline technique to obtain the most and least significant bits of the recovered data to cancel the residual intersymbol interference (ISI) sequentially. The number of data comparators is reduced to one-third compared to the typical architecture to relax the speed-power trade-offs. This paper also studies the limitation of the proposed architecture analytically. Besides, an analytical expression for the bit-error-rate (BER) with pipelined DFE is derived and validated through MATLAB-simulation to be compared with BER of the typical architecture. A 20-Gb/s inductorless receiver equalizer consisting of a linear equalizer and a one-tap DFE has been designed in 65-nm CMOS technology. Error-free operation of the equalizer has been validated by post-layout simulations over 21-inch FR4 channel with 15-dB loss at the Nyquist frequency using a PRQS-7 data pattern.

Keywords

• Analog equalization
• 4-level pulse amplitude modulation (PAM-4)
• analog receiver
• decision-feedback equalizer (DFE)
• wireline
• comparator