FPGA implementation of satellite based AIS non-coherent receiver with bandpass sampling

Abstract

The satellite based automatic identification system(AIS) receiver is known to have a narrow signal bandwidth, high Doppler frequency drift and a requirement for low complexity. This paper designs a bandpass sampling AIS noncoherent receiver on FPGA. A two-stage digital down conversion structure is adopted to reduce the FPGA processing pressure and the logic resource consumption. The digital frequency discriminator cascaded by a low pass filter is implemented to achieve non-coherent demodulation of AIS signal. In the AD9246 plus Xilinx xc4vlx80FPGA core board, the AIS signal demodulation is tested to verify our design. The proposed design consumes less resource, and is conducive to the miniaturization of AIS equipment as well as hardware costs reduction.

Keywords

• bandpass sampling
• GMSK
• non-coherent demodulation
• digital frequency discriminator
• FPGA