FPGA-based ML adaptive accelerator: A partial reconfiguration approach for optimized ML accelerator utilization

Abstract

The relentless increase in data volume and complexity necessitates advancements in machine learning methodologies that are more adaptable. In response to this challenge, we present a novel architecture enabling dynamic classifier selection on FPGA platforms. This unique architecture combines hardware accelerators of three distinct classifiers—Support Vector Machines, K-Nearest Neighbors, and Deep Neural Networks—without requiring the combined area footprint of those implementations. It further introduces a hardware-based Accelerator Selector that dynamically selects the most fitting classifier for incoming data based on the K-Nearest Centroid approach. When tested on four different datasets, Our architecture demonstrated improved classification performance, with an accuracy enhancement of up to 8% compared to the software implementations. Besides this enhanced accuracy, it achieved a significant reduction in resource usage, with a decrease of up to 45% compared to a static implementation making it highly efficient in terms of resource utilization and energy consumption on FPGA platforms, paving the way for scalable ML applications. To the best of our knowledge, this work is the first to harness FPGA platforms for dynamic classifier selection.

Keywords

• Field programmable gate array
• Partial reconfiguration
• Reconfigurable hardware
• Machine learning
• Dynamic classifier selection