A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC

Abstract

This article presents an accurate quadrature phase-locked loop (PLL) with quadrature phase mismatch calibration for 32 GS/s analog-to-digital converter (ADC). Due to the mismatches of clock distribution in layout and variations of the active devices, the quadrature phase of the sampling clock is significantly deteriorated. To solve the problem, a novel quadrature divider with phase calibration is induced in PLL loop. Moreover, a theoretical model of the quadrature divider is proposed to predict the performance and potential ability for phase calibration. Based on the theoretical and model analysis, the proposed PLL can realize accurate quadrature phase for high-speed real-time sampling system. The output frequency of PLL is 8 GHz with quadrature phases for 32 GS/s sampling rate. The proposed clock can realize 8-bit signal to noise ratio requirement with 16 GHz bandwidth. The proposed PLL was fabricated in 65-nm CMOS process with 28 mW dc power consumption under 1.2 V supply voltage. Testing results show that the phase noise of the clock is -127 dBc/Hz @10 MHz-offset frequency when the sampling speed is 27.4 GS/s. With proposed methods, the range of the phase error calibration is around ±20°.

Keywords

• Phase locked loop (PLL)
• quadrature phase
• jitter
• phase noise
• quadrature divider
• time-interleaved sampling