Design of XOR-NMOS switch based kickback noise reduction technique for dynamic comparators

Abstract

We have integrated dynamic comparators to meet the rigorous demands for ultra-low power and miniaturized ADC converters, which are essential for optimizing power efficiency, speed, and overall performance within ADC circuits. These comparators scrutinize input signal voltages against predefined reference values, with traditional dynamic comparators offering distinct advantages such as minimal power consumption, elevated input impedance, and robust noise tolerance. However, their susceptibility to kickback noise is a significant drawback, substantially hindering operational efficiency. Our innovative solution focuses on noise reduction, strategically deploying sampling switches and XOR gates between the regenerative nodes and comparator inputs to create an effective noise isolation barrier. Validation through exhaustive simulations using Mentor Graphics software within the framework of state-of-the-art 45 nm CMOS technology showcases the effectiveness of our approach. Scientifically, our work holds profound significance. Addressing the pervasive issue of kickback noise in dynamic comparators has the potential to reshape the ADC technology landscape. This advancement promises to significantly enhance the performance of existing systems, paving the way for more efficient and compact ADC converters. Our research contributes to various application domains reliant on ADC systems, marking a critical milestone in the scientific exploration of noise reduction techniques in analogue circuitry. It drives progress and fosters innovation, offering a promising vision for the future of ADC technology and its broader implications across scientific and engineering disciplines.

Keywords

• CMOS
• Comparator
• Kickback noise
• ADC