CMOS-Based Memristor Emulator Circuits for Low-Power Edge-Computing Applications

Abstract

In this paper, an optimized memristor emulator circuit is designed, by using nine MOSFET transistors and a ground capacitor. Our area- and power-optimized emulator circuit can be used for basic data storage and processing at the monitoring edge, in real-time applications. The memristor shows a nonlinear voltage–current relationship, but no multiplier circuit provides the memristor’s nonlinear characteristics. As a result, the proposed memristor emulator has a very low chip area. The memristor circuit is designed in LTSpice, using 16 nm and 45 nm CMOS technology parameters, and the operating voltage is ±0.9 V. In this research, the theoretical derivations are validated using the simulated results of the memristor emulator circuit using different frequencies, capacitors, and input voltages in SPICE simulations.

Keywords

• memristor emulator
• nonlinear resistor
• CMOS
• frequency analysis
• pinched hysteresis loop