An efficient reliability estimation method for CNTFET‐based logic circuits

Abstract

Carbon nanotube field‐effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post‐complementary metal‐oxide‐semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET‐based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.

Keywords

• cntfets
• gate‐level circuit design
• reliability estimation algorithms
• transistor‐level design