Zhejiang Daxue xuebao. Lixue ban (Sep 2003)

Tabular synthesis of three-variable functions using one-bit full adders(基于一位全加器三变量逻辑函数的查表综合)

ZHOUChang(周畅),
WUYin-er(伍银儿),
CHENXie-xiong(陈偕雄)

Affiliations

ZHOUChang(周畅): Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310028, China(浙江大学信息与电子工程系，浙江杭州 310028)
WUYin-er(伍银儿): Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310028, China(浙江大学信息与电子工程系，浙江杭州 310028)
CHENXie-xiong(陈偕雄): Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310028, China(浙江大学信息与电子工程系，浙江杭州 310028)

DOI
Journal volume & issue: Vol. 30, no. 5
pp. 518 – 523

Abstract

通过对1个一位全加器3个输入端不同的组合,可以实现与门、或门、非门、同或门及异或门,因此全加器在数字逻辑电路中有着重要的作用.本文在介绍全加器的基础上提出了用查表法设计基于一位全加器实现任意三变量函数的组合电路和时序电路.在与传统的与非门/或非门的比较中,它显示了优势.

Published in Zhejiang Daxue xuebao. Lixue ban

ISSN: 1008-9497 (Print)
Publisher: Zhejiang University Press
Country of publisher: China
LCC subjects: Science: Mathematics: Instruments and machines: Electronic computers. Computer science; Science: Physics
Website: https://www.zjujournals.com/sci/EN/1008-9497/home.shtml

About the journal