Applied Sciences (Dec 2021)

Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

  • Hayeon Jeong,
  • Huidong Lee,
  • Bonghyuk Park,
  • Seunghyun Jang,
  • Sunwoo Kong,
  • Changkun Park

DOI
https://doi.org/10.3390/app112411691
Journal volume & issue
Vol. 11, no. 24
p. 11691

Abstract

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In this study, a differential power amplifier (PA) with a high gain of over 30 dB by configuring a three-stage common source unit amplifier was designed. To ensure the stability of the high-gain differential PA, the analysis to apply the capacitive neutralization method to the differential common source PA was conducted. From the analysis, the required neutralized capacitance was quantitatively calculated from the estimated parasitic components of a power cell used in the PA. To verify the feasibility of the proposed optimization technique, a Ka-band PA was designed with a 65 nm RFCMOS process. The measurement results showed a gain of 30.7 dB. The saturated output power was measured as 16.1 dBm, maximum power-added efficiency (PAE) was 29.7%, and P1dB was 13.1 dBm.

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