Dianxin kexue (Feb 2022)
Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations
Abstract
In order to achieve the requirement of high throughput and low-power in wireless communication, a parallel Turbo decoder has attracted extensive attention.By analyzing the calculating of the state metrics, a low-resource parallel Turbo decoder architecture scheme based on merging the forward and backward state metrics calculation modules was proposed, and effectiveness of the new architecture was demonstrated through field-programmable gate array (FPGA) hardware realization.The results show that, compared with the existing parallel Turbo decoder architectures, the proposed design architecture reduces the logic resource of state metrics calculation module about 50%, while the dynamic power dissipation of the decoder architecture is decreased by 5.26% at the frequency of 125 MHz.Meanwhile the decoding algorithm is close to the decoding performance of the parallel algorithm.
