Multi-Tap FlexHtree application in high performance CPU design

Abstract

For high performance CPU design, especially on 16 nm and advanced process nodes, with the increase in the number of signoff corner, increasing the clock common path, improving the clock latency correlation on various RC corners, decreasing local skew of design, those are our common view. The Cadence innovus Flexible H-tree(FlexHtree) feature not only provides the symmetric buffer structure and equal wire lengths benefits of an H-tree, but also relaxes the requirement to be geometrically symmetric, enabling clock tree synthesis even in floorplans with sink placement. This paper presents an automatic Flexible H-tree flow to decrease clock skew on different corners. Meanwhile, this paper will discuss the impact of multi-taps counts and synthesis engines of the sub-tree on clock skew and design timing in details, then choses a better solution. Finally, in terms of timing, power consumption, and instance counts results, the design mentioned in this paper is suitable to use Flexible H-tree clock structure in comparison to CCOPT and fishbone structure clock tree.

Keywords

• FlexHtree; clock skew; clock tree
• CCOPT
• innovus