AIP Advances (Jun 2020)

Interface trap and border trap characterization for Al2O3/GeOx/Ge gate stacks and influence of these traps on mobility of Ge p-MOSFET

  • Wei-Chen Wen,
  • Yuta Nagatomi,
  • Hiroshi Akamine,
  • Keisuke Yamamoto,
  • Dong Wang,
  • Hiroshi Nakashima

DOI
https://doi.org/10.1063/5.0002100
Journal volume & issue
Vol. 10, no. 6
pp. 065119 – 065119-7

Abstract

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Interface traps (ITs) and border traps (BTs) in Al2O3/GeOx/p-Ge gate stacks were characterized using deep-level transient spectroscopy. Through evaluating the gate stacks with different GeOx thicknesses, the respective BTs in Al2O3, the Al2O3/GeOx interface region, and GeOx were detected. The density of ITs (Dit) near the midgap is lower in the metal-oxide-semiconductor (MOS) capacitors with thicker GeOx, while Dit near the valence band is lower in the MOS capacitor with thinner GeOx. The density of BTs (Nbt) in Al2O3 (6–9 × 1017 cm−3) is lower than those in GeOx (∼2 × 1018 cm−3), and the highest Nbt (∼1 × 1019 cm−3) was found in the Al2O3/GeOx interface region. Ge p-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) with Al2O3/GeOx/p-Ge gate stacks were fabricated and analyzed. We confirmed that the ITs and the BTs near the valence band edge of Ge affect the effective mobility of Ge p-MOSFETs in the high-field region.