High figure-of-merit SOI power LDMOS for power integrated circuits

Abstract

The structural modifications in the conventional power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS) are carried out to improve the breakdown voltage, on-resistance, gate-charge and figure-of-merits of the device with reduced cell pitch. The modified device has planer structure implemented on silicon-on-insulator which is suitable for low to medium voltage power integrated circuits. The proposed LDMOS consists of two gate electrodes placed vertically in two separate trenches build in the drift region and single source and drain contacts are taken on the top. The trench structure reduces the electric field inside the drift region and allow increased drift layer doping concentration leading to higher breakdown voltage, lower specific on-resistance, reduced gate-drain charge, and substantial improvement in the figure-of-merits. Using two-dimensional simulations, the performance of the proposed LDMOS is optimized and results are compared with the conventional LDMOS. Our simulation results show that the proposed device exhibits 110% higher breakdown voltage, 40% reduction in cell pitch, 19% lower specific on-resistance, 30% lower gate-to-drain charge leading to 5.5 times improvement in Baliga's figure-of-merit and 43% reduction in dynamic figure-of-merit over the conventional device.

Keywords

• Power LDMOS
• SOI
• Breakdown voltage
• On-resistance
• Figure-of-merit