An Output-Capacitorless Low-Dropout Regulator with Slew-Rate Enhancement
Shenglan Ni,
Zhizhi Chen,
Chenkai Hu,
Houpeng Chen,
Qian Wang,
Xi Li,
Sannian Song,
Zhitang Song
Affiliations
Shenglan Ni
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
Zhizhi Chen
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
Chenkai Hu
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
Houpeng Chen
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
Qian Wang
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
Xi Li
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
Sannian Song
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
Zhitang Song
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
A novel output-capacitorless low-dropout regulator (OCL-LDO) with an embedded slew-rate-enhancement (SRE) circuit is presented in this paper. The SRE circuit adopts a transient current-boost strategy to improve the slew rate at the gate of the power transistor when a large voltage spike at the output is detected. In addition, a feed-forward transconductance cell is introduced to form a push–pull output structure with the power transistor. The simulation results show that the maximum transient output voltage variation is 23.5 mV when the load current ILOAD is stepped from 0 to 100 mA in 100 ns with a load capacitance of 100 pF, and the settling time is 1.2 μs. The proposed OCL-LDO consumes a quiescent current of 30 μA and has a dropout voltage of 200 mV for the maximum output current of 100 mA.
