Spin Qubits Confined to a Silicon Nano-Ridge

Abstract

Electrostatically-defined quantum dots (QDs) in silicon are an attractive platform for quantum computation. Localized single electron spins define qubits and provide excellent manipulation and read-out fidelities. We propose a scalable silicon-based qubit device that can be fabricated by industry-compatible processes. The device consists of a dense array of QDs localized along an etched silicon nano-ridge. Due to its lateral confinement, a simple dense array of metallic top-gates forms an array of QDs with controllable tunnel-couplings. To avoid potential fluctuations because of roughness and charged defects at the nano-ridge sidewall, the cross-section of the nano-ridge is trapezoidal and bounded by atomically-flat {111} facets. In addition to side-gates on top of the low-defect oxidized {111} facets, we implement a global back-gate facilitated by the use of silicon-on-insulator. The most relevant process modules are demonstrated experimentally including anisotropic wet-etching and local oxidation of the silicon nano-ridge, side-gate formation with chemical-mechanical polishing, and top-gate fabrication employing the spacer process. According to electrostatic simulations, our device concept allows forming capacitively-coupled QD double-arrays or adjacent charge detectors for spin-readout. Defining a logical qubit or realizing a single electron conveyor for mid-range qubit-coupling will be future applications.

Keywords

• electron spin qubit
• silicon nano-ridge
• TMAH-etching
• MOS structure
• interface defects
• self-aligned spacer process
• device simulation