Cryogenic Storage Memory with High‐Speed, Low‐Power, and Long‐Retention Performance

Abstract

Abstract Cryogenic‐computing draws attention due to its variety of applications such as cloud‐computing, aerospace electronics, and quantum computing. Low temperature (e.g., 77 K) enables higher switching speed, improved reliability, and suppressed noise. Although cryogenic dynamic random‐access memory is studied, the cryogenic NAND flash is not explored intensively. Herein, a cryogenic storage memory based on the charge‐trap mechanism is reported. By removing the tunneling oxide from the conventional silicon/oxide/nitride/oxide/silicon (SONOS)‐type flash memory (therefore becoming silicon/oxide/nitride/silicon (SONS)), high‐speed and low‐power operation is aimed to be achieved while relieved from poor retention issue thanks to the cryogenic environment. The FinFET‐structured SONS memory device is demonstrated experimentally with gate length of 20–30 nm, which can achieve the retention issue (>10 years) with low voltage (≈6.5 V) and high speed (≈5 µs) operation at 77 K. To have a holistic system‐level evaluation, benchmark simulation of an interface between a host microprocessor and solid‐state‐drive is conducted, considering the refrigerator cooling cost and the heat loss via cables across two temperatures (300 and 77 K). The results show that the SONS‐type cryogenic storage system shows over 81% improvement in both latency and power, compared to the SONOS counterpart located at cryogenics.

Keywords

• charge‐trap memory
• cryogenic
• endurance
• flash memory
• retention
• silicon‐oxide‐nitride‐oxide‐silicon (SONOS)