SAT-Based Counterexample-Guided Inductive Synthesis of Distributed Controllers

Abstract

This article proposes a new method for automatic synthesis of distributed discrete-state controllers from given temporal specification and behavior examples. The proposed method develops known synthesis methods to the distributed case, which is a fundamental extension. This method can be applied for automatic generation of correct-by-design distributed control software for industrial automation. The proposed approach is based on reduction to the Boolean satisfiability problem (SAT) and has Counterexample-Guided Inductive Synthesis (CEGIS) at its core. We evaluate the proposed approach using the classical distributed alternating bit protocol.

Keywords

• Control system synthesis
• inference algorithms
• Boolean satisfiability
• counterexample-guided inductive synthesis
• formal verification
• model checking