Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms

Abstract

This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT) suitable for electronic warfare (EW) applications. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA), fast Fourier transform (FFT), large point reconfigured, signal processing system.

Keywords

• Digital receivers
• field programmable gate array (FPGA)
• fast Fourier transform (FFT)
• large point reconfigured
• signal processing system.