Conversion‐less algebraic interleaver architecture for low‐latency IDMA systems

Abstract

Abstract This letter presents a conversion‐less algebraic interleaver architecture for low‐latency interleave division multiple access (IDMA) systems. The existing architectures adopt the two‐step approach that first generates a set of sequential indices, and then converts it into a set of interleaved indices, elongating the latency. In contrast, the proposed structure directly produces the interleaved indices by employing a logic that keeps returning the next index corresponding to the current one. As a result, it can greatly alleviate the latency compared with the existing schemes in the literature.

Keywords

• application specific integrated circuits
• digital circuits
• multi‐access systems
• multiuser detection
• VLSI