IEEE Open Journal of the Communications Society (Jan 2021)

Hardware Implementation and Performance Analysis of Improved Sphere Decoder in Spatially Correlated Massive MIMO Channels

  • Dimitris Vordonis,
  • Vassilis Paliouras

DOI
https://doi.org/10.1109/OJCOMS.2021.3133014
Journal volume & issue
Vol. 2
pp. 2680 – 2694

Abstract

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Detection for high-dimensional multiple-input multiple-output (MIMO) and massive MIMO (MMIMO) systems is an active field of research in wireless communications. While most works consider spatially uncorrelated channels, practical MMIMO channels are correlated. This paper investigates the impact of correlation on Sphere Decoder (SD), for both single-user and multi-user scenarios. The complexity of SD is mainly determined by the initial radius method and the number of visited nodes during detection. This paper introduces a new constraint on the evaluation process of the partial distance thus modifying the conventional tree searching algorithm. This significantly decreases the number of visited nodes and renders SD feasible for large-scale systems. In addition, a proposed hardware implementation featured with a one-node-per-cycle architecture, minimizes the latency of the detection process. Trade-offs between bit error rate performance and computational complexity are presented. The trade-offs are achieved by either modifying the backtracking mechanism or limiting the number of radius updates. Simulation results prove that the proposed optimizations are effective for both correlated and uncorrelated channels, regardless of the level of noise. The decoding gain of SD compared to the low-complexity linear detectors is higher in the presence of correlation than in the uncorrelated case. However, as expected, spatial correlation adversely affects the performance and the complexity of SD. Simulation results reported here also confirm that correlation at the side equipped with more antennas is less detrimental. Hardware implementation aspects are examined for both a Virtex-7 field-programmable gate array device and a 28-nm application-specific integrated circuit technology.

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