Information Engineering Group, Department of Engineering and Social Sciences (CECS), Federal University of ABC (UFABC), Av. dos Estados, 5001, Santo André 09210-580, Brazil
Oswaldo Hideo Ando
Academic Unit of Cabo de Santo Agostinho (UACSA), Federal Rural University of Pernambuco (UFRPE), Cabo de Santo Agostinho 54518-430, Brazil
Hugo Puertas de Araújo
Information Engineering Group, Department of Engineering and Social Sciences (CECS), Federal University of ABC (UFABC), Av. dos Estados, 5001, Santo André 09210-580, Brazil
Mario Gazziro
Information Engineering Group, Department of Engineering and Social Sciences (CECS), Federal University of ABC (UFABC), Av. dos Estados, 5001, Santo André 09210-580, Brazil
This work introduces a novel custom-designed 16-bit RISC-V processor, intended for educational purposes and for use in low-resource equipment. The implementation, despite providing registers of 16 bits, is based on RV32E RISC-V ISA, but with some key differences like a reduced instruction set that is optimized for embedded systems, the removal of floating-point instructions, reduced register count, and modified data types. These changes enable the processor to operate efficiently in resource-constrained environments while still maintaining assembly-level compatibility with the standard RISC-V architecture. The educational aspects of this project are also a key focus. By working on this project, students can gain hands-on experience with digital logic design, Verilog programming, and computer architecture. The project also includes tools and scripts to help students transform assembly code into binary format, making it easier for them to test and verify their designs. Additionally, the project’s open-source nature allows for collaboration and the sharing of knowledge among students and researchers worldwide.
