Design methodology for digital active disturbance rejection control of the DC motor drive

Abstract

Digital active disturbance rejection controllers (DADRC) have a wide scope as they have inherent advantages such as: easy hardware implementation, the entire system's mathematical model it is not necessary, is a linear controller dealing with uncertainty and is intended to ensure that energy savings are achieved. This document provides a procedure for designing a DADRC for a dc motor drive from the perspective of a Generalized Proportional Integral observer and differential flatness. The angular speed of a dc motor drive is the main purpose of the controller. The proposed DADRC was implemented using floating point operations on a field programmable gate array Artix-7™ using a Nexys 4 board. The system is subject to current demands, parameter variations, dc power supply changes and external load torque variations. The coupling of buck converter and dc motor resulting in external and internal disturbances that are actively counteracts the linear controller, as shown in the results.

Keywords

• Control engineering computing
• Digital programmable control
• Embedded software
• Field programmable gate arrays
• Motor drives
• Power system control