Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices

Abstract

Adoption of IoT technology without considering its security implications may expose network systems to a variety of security breaches. In network systems, IoT edge devices are a major source of security risks. Implementing cryptographic algorithms on most IoT edge devices can be difficult due to their limited resources. As a result, compact implementations of these algorithms on these devices are required. Because the field multiplication operation is at the heart of most cryptographic algorithms, its implementation will have a significant impact on the entire cryptographic algorithm implementation. As a result, in this paper, we propose a small hardware accelerator for performing field multiplication on edge devices. The hardware accelerator is primarily composed of a processor array with a regular structure and local interconnection among its processing elements. The main advantage of the proposed hardware structure is the ability to manage its area, delay, and consumed energy by choosing the appropriate word size l. We implemented the proposed structure using ASIC technology and the obtained results attain average savings in the area of 95.9%. Also, we obtained significant average savings in energy of 63.2%. The acquired results reveal that the offered hardware accelerator is appropriate for usage in resource-constrained IoT edge devices.

Keywords

• Finite field multiplication
• IoT security
• Cryptography
• IoT-edge devices
• Parallel processing
• Processor array