Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application

Abstract

With the growing popularity of FPGA-based accelerators in HPC applications, new challenges have emerged, particularly in terms of programming and portability. This paper provides an overview of the current state of FPGA tools and their limitations. This study evaluates the performance and portability of two frameworks, SYCL and OpenCL, for developing HPC FPGA solutions. The case of porting a highly-parallel application to FPGAs is studied. First, naïve, low-development-effort implementations are presented using both ND-range and single-task types of kernels, and their performance is evaluated. Subsequently, an optimized FPGA-centric approach is presented and assessed using metrics from the compilation framework. Finally, the different approaches presented are implemented using OpenCL and SYCL and their performance is evaluated. Results reveal that ND-range kernels offer high portability for highly parallel applications, while single-task codes exhibit significantly lower portability. Additionally, SYCL struggles to generate efficient hardware architectures for this kind of application when described as single-task codes, although its performance when following the ND-range approach is surprisingly high.

Keywords

• Data parallelism
• FPGA
• HLS
• OpenCL
• portability
• SYCL