Tunable Multilevel Gate Oxide Capacitance and Flat‐Band Voltage Shift Characteristics by Filament Formation in Double‐Floating‐Gate Metal–Oxide–Semiconductor Capacitors

Abstract

Abstract Tunable multilevel gate oxide capacitance and flat‐band voltage shift characteristics in double‐floating‐gate metal–oxide–semiconductor (DFG‐MOS) capacitors are investigated for non‐volatile memory and programmable logic device applications. The DFG‐MOS capacitor with the structure of Ag(control gate)/CeO2(upper control oxide)/Al(upper FG)/CeO2(lower control oxide)/Pt(lower FG)/HfO2(tunneling oxide) on n‐Si substrate, that is Ag/CeO2/Al/CeO2/Pt/HfO2/n‐Si, exhibits three capacitance states as a result of reversible formation and rupture of conducting filaments at serially stacked Ag/CeO2/Al and Al/CeO2/Pt capacitors upon applying positive and negative gate voltages, respectively. In contrast, the DFG‐MOS capacitor with Ag/CeO2/Pt/HfO2/Pt/HfO2/n‐Si employing inert Pt upper and lower FGs exhibits two capacitance states via the formation and rupture of filament only at the upper Ag/CeO2/Pt stack. Instead, it accompanies a flat‐band voltage shift by electrical charging at the lower FG of Pt. The proposed devices operate with tunable multilevel gate oxide capacitance and flat‐band voltage shift associated with filament formation inside gate stacks and electrical charging with respect to the constituent materials of the FGs. These results pave the way for potential application to non‐volatile memory and programmable MOSFET logic device with tunable gate oxide capacitance, without relying solely on the electrical charging used in the current flash‐type memory.

Keywords

• double‐floating‐gate metal–oxide–semiconductor
• filament formation
• flat‐band voltage shift
• tunable multilevel capacitance