Analog IC Design Using Precomputed Lookup Tables: Challenges and Solutions

Abstract

Design productivity remains an important aspect in the analog integrated circuit design industry, as growing competition and shorter design cycles pressure the traditional flow that involves time-consuming manual iterations in a circuit simulator. This paper describes innovations within an alternative framework that uses precomputed look-up tables (LUTs) to enable fast and accurate evaluation of circuit sizing scenarios without a simulator in the loop. It lets the designer explore and understand the design space boundaries in a systematic setting, thus supporting informed decision making and architectural innovation that is difficult to attain with fully automated, black-box sizing tools. Our discussion begins with an overview of the LUT-based design paradigm and its two primary variants: inverse design (finding design parameters that meet the specifications) and forward evaluation (sweeping design parameters to search the design space). In support of the latter, the core of our work focuses on improving the accuracy and speed of LUT access, enabling millions of queries within seconds on a standard computer. Large improvements over prior art are enabled using enhanced interpolation methods, which allow for a relatively large LUT grid spacing (hence small memory footprint) and yet accurate parameter lookup. We evaluate the efficacy of the proposed methods using two classical analog circuits, a bandgap reference and a folded cascode amplifier. In the bandgap example, we observe less than 1 ppm error between the LUT-predicted temperature coefficient and circuit simulation. In the folded-cascode example, one million design points are generated in only 4 seconds, providing the designer with useful maps that delineate the reachability of certain target specifications.

Keywords

• Systematic analog design
• precomputed lookup tables
• gm/ID methodology
• analog design automation
• interpolation
• bandgap voltage reference