An Improved Strong Arm Comparator With Integrated Static Preamplifier

Abstract

This paper presents a novel Strong Arm comparator in which the input pair is reused as a static amplifier to preamplify the input signal during the precharge phase. The proposed approach relaxes the main trade-offs that characterize the Strong Arm latch: compared to the conventional topology, the enhanced comparator achieves better input-referred noise and offset, without penalizing delay nor power consumption. In fact, the proposed topology is even more efficient than its conventional counterpart as it exhibits lower power consumption when the two circuits are sized to have the same delay. The operation of the new topology is analyzed in detail through a comprehensive theoretical analysis, providing useful design criteria. The enhanced Strong Arm comparator is validated by means of post-layout simulations in a 55 nm CMOS technology with 1 V supply. The simulations show that the proposed approach improves noise, offset and energy-delay product (EDP) respectively by 28.5%, 33.8% and 5.24% compared to the conventional Strong Arm latch.

Keywords

• Strong Arm
• high speed
• dynamic comparator
• analog-to-digital conversion (ADC)