Hardware performance analysis of RSA cryptosystems on FPGA for wireless sensor nodes

Abstract

In order to enhance the speed with good flexibility and physical security of design it is required to implement public key cryptographic algorithm on reconfigurable devices. The dedicated accelerators or coprocessors are combined with hardware solutions to support high-speed data cryptographic techniques in wireless sensor nodes. Two architectures are proposed (a) RSA-CIPHER128 and (b) mMMM42 to check the appropriateness for implementation in Wireless Sensor Nodes. Synthesis and simulation of VHDL code is carried out using Xilinx-ISE for the architectures. Results are obtained on different FPGA devices to compare the performance with speed and area. RSACIPHER128 multiplier gives the good execution speed. Where area is not a constraint, RSA cryptosystem with mMMM42 is appropriate for Wireless Sensor Network(WSN) nodes. Cryptosystem with mMMM42 consumes adoptable hardware in FPGA for WSN nodes. On Atrix-7 device the cryptosystem with RSA-CIPHER128 gives less area utilization and mMMM42 delivers good throughput. This trade-off between the design metrics leads to the designer to select the architecture depending on the applications. Throughput achievement with utilization of Slices(TPS) and LUTs(TPL) is analyzed to evaluate the performance of architectures.

Keywords

• Artix-7
• FPGA
• RSA-CIPHER128
• mMMM42
• TPS
• TPL