Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

Abstract

This paper proposes a discrete multi-tone timing-recovery system with adaptive equalization for ultra-high-speed wireline applications. It combines frequency-domain clock recovery with decision-directed equalization to improve receiver performance while eliminating the need for pilot carriers, thereby increasing spectral efficiency. Compared to a conventional pilot-carrier-based technique employing four pilot carriers and a 32-point FFT, this approach improves phase-error sensitivity by 3.6 times, tracking bandwidth by 1.7 times, increases the jitter tolerance slope by $20dB$ per decade at low frequency, and removes residual equalization error, resulting in an overall data-rate increase of 27%. The concept is validated at the system-level and gate-level through synthesis in an FPGA. A convergence analysis of both the adaptive equalizer and clock synchronization shows the system’s ability to mitigate error propagation and remain synchronized in the presence of impairments. Finally, we highlight the system’s ability to trade-off clock convergence versus phase error sensitivity. Either parameter can be adjusted by 15 times, optimizing the receiver over a broad range of signal conditions.

Keywords

• Adaptive equalization
• clock and data recovery (CDR)
• decision-directed equalization
• discrete multi-tone (DMT)
• orthogonal frequency division multiplexing (OFDM)
• SERDES