Design of ternary full-adder and full-subtractor using pseudo NCNTFETs

Abstract

Now-a-days, the binary logic system has intensified by scaling the field effect transistor (FET). However, due to the effectiveness of scaling the FET, ternary logics became more popular. Out of numerous ternary logic devices, carbon nanotube (CNT) FET (CNTFET) is considered a good candidate over silicon FETs. Hence, in this study, ternary schematics are developed based on Pseudo N-type CNTFETs. The ternary basic designs such as standard ternary inverter (STI), AND and OR gates are presented. Then, using the proposed basic logic gates, the complex designs such as full adder and full subtractor are also proposed. The HSPICE simulator is utilized to design proposed circuits and analyze different performance parameters. The performance such as delay, power and power delay product (PDP) are analyzed for the proposed circuits. Moreover, the proposed schematics performances are also compared to complementary schematics. It investigated that Pseudo N-type CNTFET schematics improved the overall performance on an average up to 65.82% over the complementary ternary circuits.

Keywords

• Ternary
• Pseudo N-CNTFETs
• Full adder
• Full subtractor and HSPICE