Optimization of PLL frequency synthesizer

Abstract

The influence of different configurations of phase-locked loop frequency (PLL) with integer coefficients on parameters of the PLL loop of the frequency synthesizer is considered. The possibility of computer prediction of such PLL parameters as power consumption, start-up time, jitter and phase noise level at the choice of the frequency divider from the generator to the circuit output is shown.

Keywords

• frequency synthesizer
• pll
• voltage-controlled oscillator
• reference oscillator