A 13-Bit 1-MS/s SAR ADC With Completion-Aware Background Capacitor Mismatch Calibration

Abstract

This paper introduces a completion-aware background sequential capacitor mismatch calibration technique for SAR ADC. The proposed method sequentially corrects capacitor mismatch from the lower to the upper bits in the CDAC. This calibration method can automatically detect when calibration is complete, thereby improving power efficiency by terminating calibration activities. This approach mitigates the trade-off between adaptation speed and calibration code variation, enhancing correction speed. Moreover, the sequential calibration demonstrates stable adaptation in unpredictable input environments. The ADC developed in this study utilizes 55-nm ultra-low power (ULP) CMOS technology, operates at a speed of 1 MS/s, and consumes $43~\mu W$ of power. It achieves peak DNL of +0.83/−0.62 LSB and INL of +1.89/−1.13 LSB. Furthermore, it achieves a mean SNDR of 68.5 dB and SFDR of 83.8 dB, resulting in a FoM of 19.59 fJ/conv.-step.

Keywords

• Analog-to-digital converter (ADC)
• successive approximation register (SAR)
• capacitor mismatch
• background calibration