Grant‐Aware Scheduling Algorithm for VOQ‐Based Input‐Buffered Packet Switches

Abstract

In this paper, we propose a grant‐aware (GA) scheduling algorithm that can provide higher throughput and lower latency than a conventional dual round‐robin matching (DRRM) method. In our proposed GA algorithm, when an output receives requests from different inputs, the output not only sends a grant to the selected input, but also sends a grant indicator to all the other inputs to share the grant information. This allows the inputs to skip the granted outputs in their input arbiters in the next iteration. Simulation results using OPNET show that the proposed algorithm provides a maximum 3% higher throughput with approximately 31% less queuing delay than DRRM.

Keywords

• Grant‐aware
• High performance
• Input‐buffered switch
• Scheduling
• Low latency
• Maximal matching algorithm