9T fast‐write SRAM bit cell with no conflicts for ultra‐low voltage

Abstract

Abstract With the development of processes and reduction of transistor size, transistor sensitivity to voltage changes has increased. Traditional SRAM bit cells struggle to function properly at low voltages, and the lengthy write time necessitated by the write conflict problem will inevitably result in write failure. As ultra‐low‐voltage SRAM has emerged as a significant direction of research for SRAM, this paper proposes an ultra‐low‐voltage 9T SRAM bit cell that is conflict‐free. By circumventing write conflicts and enabling rapid writing, the bit cell demonstrates its superiority, particularly at ultra‐low voltages, by eliminating the requirement for peripheral write‐assist circuitry to accomplish chip writing. To assess the performance of the conflict‐free 9T bit cell, simulation experiments are conducted utilizing the 28 nm process model. Simulation results indicate that the 9T bit cell proposed in this paper requires only 66% of the writing time of the traditional 6T cell. This enables the cell to accomplish fast writing and more stable writing performance.

Keywords

• circuit simulation
• CMOS memory circuits