Mode I Fatigue and Fracture Assessment of Polyimide–Epoxy and Silicon–Epoxy Interfaces in Chip-Package Components

Abstract

Semiconductor advancements demand greater integrated circuit density, structural miniaturization, and complex material combinations, resulting in stress concentrations from property mismatches. This study investigates the failure in two types of interfaces found in chip packages: silicon–epoxy mold compound (EMC) and polyimide–EMC. These interfaces were subjected to quasi-static and fatigue loading conditions. Employing a compliance-based beam method, the tests determined interfacial critical fracture energy values, (GIC), of 0.051 N/mm and 0.037 N/mm for the silicon–EMC and polyimide–EMC interfaces, respectively. Fatigue testing on the polyimide–epoxy interface revealed a fatigue threshold strain energy, (Gth), of 0.042 N/mm. We also observed diverse failure modes and discuss potential mechanical failures in multi-layer chip packages. The findings of this study can contribute to the prediction and mitigation of failure modes in the analyzed chip packaging. The obtained threshold energy and crack growth rate provide insights for designing safe lives for bi-material interfaces in chip packaging under cyclic loads. These insights can guide future research directions, emphasizing the improvement of material properties and exploration of the influence of manufacturing parameters on delamination in multilayer semiconductors.

Keywords

• semiconductors
• bi-material interface
• interfacial fracture
• fatigue crack growth
• Paris law curve