Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

Abstract

Abstract Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low‐cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32‐bit data‐path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple‐bit (byte) simultaneous faults at each pipeline stage’s logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault‐masking capability for multiple‐bit (byte) faults. Finally, it is shown that the Application‐Specific Integrated Circuit implementation of the fault‐tolerant architectures using the composite field‐based S‐box, CFB‐AES, and ROM‐based S‐box, RB‐AES allows better area usage, throughput and fault resilience trade‐off compared to their counterparts. So, it provides the most appropriate features to be used in highly‐secure resource‐constraint applications.

Keywords

• cryptography
• field programmable gate arrays
• fault tolerance
• error correction
• telecommunication security
• data communication