A 56 Gbps 4‐tap PAM‐4 direct decision feedback equaliser with negative capacitance employing dynamic CML comparators in 65‐nm CMOS

Abstract

Abstract Here, a 4‐level pulse amplitude modulation direct decision feedback equaliser (DFE) with a novel dynamic current‐mode‐logic comparator (DCMLC) is presented. The DCMLC breaks the trade‐off between settling time and regeneration time in traditional CML comparator design by utilizing dynamic logic and separately optimizes the tracking stage and regeneration stage for a correct latch operation at ultrahigh speed. Compared with the traditional CML comparator, the DCMLC reduces delay by 36% and has better input sensitivity on high baud rates at the cost of 7% shrunk output swing. The negative capacitance is adopted to achieve a 0.5 dB bandwidth extension ratio of up to 1.89. The reduced delay and wider bandwidth of the proposed comparator allow the implementation of 4‐tap direct DFE at 56 Gbps with 2.8 pJ/bit energy efficiency and an active area of 0.007 mm2 in 65‐nm CMOS technology.

Keywords

• Analogue circuit design, modelling and testing
• Logic circuits
• Other analogue circuits
• Semiconductor integrated circuit design, layout, modelling and testing
• CMOS integrated circuits