Templated dewetting of single-crystal sub-millimeter-long nanowires and on-chip silicon circuits

Abstract

Fabricating defect-free micro- and nano-circuits over large scales with controlled interconnections remains a challenge. Here, Bollani et al. show a dewetting strategy for engineering arrays of parallel Si-based nanowires up to 0.75 mm and complex interconnected circuits of monocrystalline Si on a chip.