Fully passive noise‐shaping successive approximation register analog‐to‐digital converter realizing 2 × gain without capacitor stacking

Abstract

Abstract The fully passive noise shaping (NS) successive approximation register (SAR) analog‐to‐digital converters (ADCs) are simple, operational transconductance amplifier (OTA) free and scaling friendly. Previous passive NS‐SAR ADCs rely on the multi‐path‐input comparator or capacitors stacking to realize the passive gain for compensating the signal attenuation during passive integration. However, the former causes high comparator power consumption, and the latter suffers from additional signal attenuation due to the parasitics and is hard to extend to high‐order systems. This work proposes a new fully passive NS‐SAR technique, it can realize 2 × gain with a simple structure, leading to the reduced comparator power, and less parasitics. This technique is also easy to extend to high‐order NS‐SAR ADCs.

Keywords

• analogue circuits
• analogue‐digital conversion
• comparators (circuits)
• integrated circuit design