The optimization and design of SCL decoding algorithm based on FPGA

Abstract

In recent years, the contribution of polarization code to communication field is becoming more and more prominent, because the theory of polarization code is proved to be able to achieve the channel limit capacity in BDMC. The decoding system of polarization codes can be realized by software or hardware, and the software decoding speed is limited by the CPU serial working mode. So it is of great value for the communication filed to implement the decoder of polarization code on FPGA with parallel working mode. Firstly the SCL decoding algorithm is introduced in this paper. Then the algorithm is optimized to improve the decoding efficiency, and the quantization improvement is carried out on FPGA. Finally, the hardware emulation of the decoder and the performance analysis are carried out on FPGA. The experimental results show that the maximum frequency of the decoder is up to 143.988 MHz, and the throughput is up to 28.79 Mb/s when the code length is 512.

Keywords

• polarization code
• FPGA
• SCL decoding
• fixed-point quantitative